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About
I am a tenured professor at the Faculty of Electrical Engineering, University of Ljubljana. My research interests include

• Optimization algorithms
• Analog and mixed-signal circuit simulation
• Circuit design automation
• Free and open source software

Teaching

• Analog electronics
• Linear electronics
• Microprocessor systems in telecommunications
• Circuit analysis and optimization
• Optimization in EDA

Software I work on

• SPICE OPUS circuit simulator (free, but closed source)
• PyOpus design automation library (homepage, on Codeberg)
• OpenVAF Verilog-A compiler
• VACASK circuit simulator
• Verilog-A Distiller model converter

• Ngspice (device models)
• Xschem (symbols)