Building a circuit from toplevel subcircuits

ground 0 

load "resistor.osdi"

// Default toplevel subcircuit
model resistor resistor
model vsource vsource

parameters pg=0

v1 (1 0) vsource dc=10
r1 (1 2) resistor r=1k
r2 (2 0) resistor r=9k

// Extra parallel resistor in parallel with v1
subckt par1()
  parameters p1=10
  rp1 (1 0) resistor r=10k
ends

// Extra parallel resistor in parallel with r2
subckt par2()
  parameters p2=20
  rp2 (2 0) resistor r=9k
ends

control
  abort always 

  options rawfile="binary" op_debug=0

  // default build
  analysis op1 op 

  // Add parallel resistor with par1
  elaborate circuit("par1")
  analysis op2 op

  // Add two parallel resistors (par1 and par2)
  elaborate circuit("par1", "par2")
  analysis op3 op
  print hierarchy
  print variables

  postprocess(PYTHON, "runme.py")
endc

embed "runme.py" <<<FILE
from rawfile import rawread
from runtest import *
import numpy as np
import sys

tests=[]

op1 = rawread('op1.raw').get()

v = op1["1"]
exact = 10
status = (relDiff(v, exact, 1e-6) < 1e-3).all()
print("op1 V(1)=", v, "exact=", exact, status)
tests.append(status)
v = op1["2"]
exact = 10*0.9
status = (relDiff(v, exact, 1e-6) < 1e-3).all()
print("op1 V(2)=", v, "exact=", exact, status)
tests.append(status)


op2 = rawread('op2.raw').get()

i1 = -op2["v1:flow(br)"]
exact = 10/10e3*2
status = (relDiff(i1, exact, 1e-12) < 1e-3).all()
print("op2 I(V1)=", i1, "exact=", exact, status)
tests.append(status)


op3 = rawread('op3.raw').get()

v2 = op3["2"]
i1 = -op3["v1:flow(br)"]
exact = 9.0/2/(1.0+9.0/2)*10.0
status = (relDiff(v2, exact, 1e-6) < 1e-3).all()
print("op3 V(2)=", v2, "exact=", exact, status)
tests.append(status)
exacti = 10.0/10e3 + 10.0/(1.0e3+9.0e3/2)
status = (relDiff(i1, exacti, 1e-12) < 1e-3).all()
print("op3 I(V1)=", i1, "exact=", exacti, status)
tests.append(status)

if isTest():
    sys.exit(not all(tests))
>>>FILE


