Test output

load "output.va"
load "capacitor.osdi"

model res resistor
model cap capacitor
model vsrc vsource

v1 (1 0) vsrc dc=0 type="pulse" val0=0 val1=1 delay=1m rise=1u
c1 (1 0) cap c=0.1u
r1 (1 0) res r=10k 

control
  abort always
  analysis tran1 tran step=0.1m stop=10m maxstep=0.1m
endc

embed "output.va" <<<FILE
`include "constants.vams"
`include "disciplines.vams"

module resistor(A,B);
	inout A, B;
	electrical A, B;
	
	branch (A,B) br;
	
	(*desc= "Resistance", type="instance", units = "Ohm"*) parameter real r = 1 from [0:inf];
	
	analog begin
        $error("Error: t=%e V(br)=%e some=%e", $abstime, V(br), 1024);
        $warning("Warning: t=%e V(br)=%e some=%e", $abstime, V(br), 1024);
        $info("Info: t=%e V(br)=%e some=%e", $abstime, V(br), 1024);
        $display("Display: t=%e V(br)=%e some=%e", $abstime, V(br), 1024);
        $strobe("Strobe: t=%e V(br)=%e some=%e", $abstime, V(br), 1024);
        $monitor("Monitor: t=%e V(br)=%e some=%e", $abstime, V(br), 1024);
        $debug("Debug: t=%e V(br)=%e some=%e", $abstime, V(br), 1024);
        $write("Write: t=%e V(br)=%e some=%e\nAfter newline\n", $abstime, V(br), 1024);
        I(br) <+ V(br)/r;
        if ($abstime>=0) begin
            $finish(0);
        end
	end
endmodule
>>>FILE
