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CACD Group
updated 2003.05.15

bullet Screenshots

Spice Opus in Action

bullet About SpiceOpus

SpiceOpus is a circuit simulator with optimisation utilities. It is a recompilation of the original Berkeley's source code for Windows 95/98/NT and Linux operating systems. Georgia Tech Research Institute's XSPICE mixed-mode simulator was added to the Berkeley code. The XSPICE code model feature was enhanced so that code models can be loaded from dll/so files (.cm files). The simulator includes an interpreted programming language called Nutmeg, which allows interactive SPICE sessions. Numerous memory leaks were fixed. The graphical part of the program was rewritten but the original syntax of the plot and iplot commands was preserved, enabling any script compatibility with other SPICE compilations. We are constantly updating SpiceOpus with new semiconductor models and we are working very hard to make it as stable as possible.

All the above however is just the foundation for our actual research work. We are interested in professional applications of different optimization methods in circuit simulation. Unfortunately there is a host of small memory leaks in any "blood relative" of Berkeley's SPICE, which are usually harmless since the operating system always reclaims allocated memory after an application closes. Serious optimization however needs hundred thousands of continuous simulation runs without choking the memory management system. Therefore we had to develop a very stable simulator before we could even think of optimization.

Our main scientific input to SpiceOpus is an optimization tool including ten different optimization approaches. The user can choose between steepest descent, Newton's method, Davidon-Fletcher-Powell's method, random search, grid search, search along coordinate axes, Powell's method, Hooke-Jeeves's method, constrained simplex, simple genetic algorithm and evaluation of cost function across whole parameter space. Each method has its own set of parameters and they can be combined via NUTMEG scripts. In addition to all these options the users has to identify suitable optimization parameters including some sensible constrains, he has to express his design criterions through a scalar cost function, which will be eventually minimized by the selected method. The whole optimization procedure is not exactly something a novice would want to tackle. It even takes experts some time (and nerves) before the optmization yields any useful results.

SpiceOpus saw its first free release in December 1999 (version 1.0). Very quickly a large user community developed, showering us with valuable feedback from all sorts problems. As you can see from the release history below we have been very busy. The optimization tool of SpiceOpus has caught quite a lot of attention from professional designers requiring more demanding individual support. In spring 2001 we therefore decided to fork a professional version SpiceOpus pro 2.1, to be released and supported by SimShelf International and keep our free release SpiceOpus light 2.1 in the research domain. The light version has no optimization tool, a limited circuit size to 300 nodes and no user support. Other than that, both versions are functionally identical and will benefit from a joined future development.

The light version should satisfy everybody involved in teaching / learning as well as companies doing board level design. Chip designers with some healthy optimization ambitions and large scale board developers on the other hand should refer to SimShelf International for the professional version including sound customer service.

bullet Release history

  • Version 2.2 (date built: 15. May 2003)
    • Command line option -c added. Under Linux it starts SPICE in console mode. Under Windows SPICE window is not opened and SPICE runs as a hidden application that can be seen only in the task manager. When this option is given, plotting, GUI functions, and the command line history using the cursor up/down keys are disabled.
    • Command line option -pl < path> added. It overrides the SPICE lib directory setting read from the environmental variable SPICE_LIB_DIR. SPICE_LIB_DIR/scripts/spinit is the spice init script file that is sourced at startup.
    • Command line option -pe < path> added. It overrides the SPICE executable directory setting read from the environmental variable SPICE_EXEC_DIR.
    • Command line option -pk < name> added (professional version only). It overrides the default lock file name (lock). The lock file is searched in the following directories:
      1. current directory,
      2. SPICE_LIB_DIR,
      3. SPICE_LIB_DIR/scripts,
      4. SPICE_EXEC_DIR
    • Command line option -gf < number> added. It overrides the SPICE default font size for the terminal window (10).
    • Option pziter added to set number of iterations in pole-zero analysis.
    • Abbreviation .inc for .include is now accepted. If the filename in .include line is embraced with single quotes then the quotes are ignored. Aliases .macro and .eom for .subckt and .ends are also accepted. .protect and .unprotect directives known in other Spices are ignored since they are irrelevant in SpiceOpus. Inline comments beginning with character $ are allowed in non-command lines. The text after the $, including $ character, is considered as a comment.
    • Option scale implemented for resistor, geometric junction diode and BSIM3v3 MOSFET models.
      Resistor model:       wscaled = w * scale
      lscaled = l * scale
      Geometric junction diode model: areascaled = area * scale2
      MOSFET model:
      (only BSIM3v3)
      wscaled = w * scale
      lscaled = l * scale
      pdscaled = pd * scale
      psscaled = ps * scale
      adscaled = ad * scale2
      asscaled = as * scale2
      Note that option scale is not implemented for other models yet.
    • The gmin implementation across the bulk diodes for MOS1, MOS2, MOS3, MOS6 and BSIM3v3 MOSFET models fixed.
    • Nutmeg commands copyplot, scktreparse and scktparams added.
    • Source lifting and improved source and gmin stepping algorithms implemented to aid convergence.
    • Option discrete_space added to optimize options command to make optimisation parameter space discrete. Grid for each optimisation parameter is defined by incremental step. It is given by increment value in parameter declaration, that is in optimize parameter command. Therefore also increment item was added to optimize parameter command.
    • Model parameter check added to BSIM3v3 MOSFET model (level=53). The default value is 1, which means that model parameter check is performed. To skip model parameter check define check=0.
    • Keyword delete added to nodeset and ic commands for removing all nodesets and initial conditions.
    • Geometric junction diode model added as level=3. Diode's length and width can be specified with instance parameters w and l. Area is then calculated by area = w * l.
    • UFET and UFSOI (University of Florida) MOSFET models added as level=7 and 58.
    • HFET model developed by Micheal Shur and Trond Ytterdal was added. It is specified as level=2 in .model statement for MESFET device.
    • STAG (Southampton Thermal Analogue) partially depleted SOI MOSFET model added as level=57. Versions 2.1 and 2.6 are available and can be selected through version model parameter.
    • Bug when writing and loading output raw files in binary mode was fixed.
    • Prefix x added as a synonym for meg = 1e6.
    • Instance parameter m (number of devices in parallel) added for all available device models and all available levels of a particular model included in SpiceOpus. Default value is always: m=1.
    • Different versions of BSIM4 MOSFET device model was added for compatibility reasons. It is specified as level=60 in .model statement. Level 8 is therefore cancelled. Different versions (4.0, 4.1, 4.2 or 4.2.1) can be chosen with version flag in .model statement. The default version is 4.2.1 which means BSIM4v4.2.1 model.
    • Different versions of BSIM3 version 3 MOSFET device model was added for compatibility reasons. It is specified as level=53 in .model statement. Level 7 is therefore cancelled. Different versions (3.0, 3.1, 3.2, 3.2.2, 3.2.3 or 3.2.4) can be chosen with version flag in .model statement. The default version is 3.2.4 which means BSIM3v3.2.4 model.
    • Different versions of BSIM3SOI version 2 MOSFET device model were added for compatibility reasons. They are specified as level=56 in .model statement. Levels 9, 10 and 11 are therefore cancelled. Different modes (partially, dynamically and fully depleted mode) are available and can be selected by soimod model parameter. soimod equals 1, 2 or 3 for partially, dynamically and fully depleted mode respectively. Versions 2.0 and 2.1 are available for dynamically and fully depleted modes. For partially depleted mode versions 2.0, 2.0.1, 2.1, 2.2, 2.2.1, 2.2.2 and 2.2.3 are included. A particular version can be chosen by version model parameter. The default value for soimod = 2, and the default version is 2.1 for dynamically and fully depleted modes and 2.2.3 for partially depleted mode.
    • Automatic model selection (binning) for BSIM3v3 MOSFET device model.
    • Graphical user interface gui command added. Its syntax is gui <command>. Therefore the exact knowledge of syntax for a particular Nutmeg command is no longer needed. For now gui is available only with commands show and optimize.
    • To modify vectors in const plot from another plot, user has to give complete vector name. Example: let const.vector_name = ....
    • Option centering added to the optimisation options. It enables optimisation procedure considering parameter tolerances. Therefore abstol and reltol items were added to optimize parameter command.
    • Procedure cost_profile added as an optimisation method. The procedure enables a view into cost function behaviour at the current circuit parameter values.
    • The BSIM3SOI version 1 MOSFET device model was added for compatibility reasons. It is specified as level=55 in .model statement. Different versions (1.0, 1.1, 1.2 or 1.3) can be chosen with version flag in .model statement. The default version is 1.3 which means BSIM3SOIv1.3 model.
    • Added area() and integrate() functions.
    • Extended syntax for resistance and capacitance instances. For resistances it introduces temperature coefficients tc1 and tc2 as instance parameters which overwrite temperature coefficients given in resistance model. New syntax is:

         r<name> <positive_node> <negative_node>
            {[<model_name>] [[r[esistance]=]<value>]} [[tc[1]=]<value>]
            [[tc2=]<value>] [l=<value>] [w=<value>] [temp=<value>] [m=<value>]

         c<name> <positive_node> <negative_node>
            {[<model_name>] [[c[apacitance]=]<value>]} [ic=<value>]
            [l=<value>] [w=<value>] [m=<value>]

         <>
         user defined field
         []     optional field
         {}     at least one filed must be specified

    • Some additional parameters were implemented into the following models:
         resistance model
            res   default resistance
         diode model
            mj (alias for m)   area junction grading coefficient
         MOS1 model
            wd   lateral diffusion into channel width from bulk
            xl   length bias accounts for masking and etching effects
            xw   width bias accounts for masking and etching effects
            delvto (alias for delvt0)   zero-bias treshold voltage shift
            n   emission coefficient
            bex   low field mobility temperature exponent
         MOS2 model
            wd   lateral diffusion into channel width from bulk
            xl   length bias accounts for masking and etching effects
            xw   width bias accounts for masking and etching effects
            delvto (alias for delvt0)   zero-bias treshold voltage shift
            n   emission coefficient
            utra   transverse field coefficient
            bex   low field mobility temperature exponent
         MOS3 model
            wd   lateral diffusion into channel width from bulk
            xl   length bias accounts for masking and etching effects
            xw   width bias accounts for masking and etching effects
            delvto (alias for delvt0)   zero-bias treshold voltage shift
            n   emission coefficient
            bex   low field mobility temperature exponent
         BSIM3v2 model
            ld (alias for dl)   channel length reduction in meters
            wd (alias for dw)   channel width reduction in meters
            php (alias for pbsw)   source drain side junction capacitance built in potential
            xl   channel length reduction in meters due to masking and etching effects
            xw   channel width reduction in meters due to masking and etching effects
            lmlt   length shrink factor
            wmlt   diffusion layer and width shrink factor
            rs   source ohmic resistance
            rsc   additional source resistance due to contact resistance
            rd   drain ohmic resistance
            rdc   additional drain resistance due to contact resistance
            jsw   sidewall bulk junction saturation current
            is   bulk junction saturation current
            n   emission coefficient
            cbd   zero bias bulk-drain junction capacitance
            cbs   zero bias bulk-source junction capacitance
            tt   transit time
         BSIM3v3 model
            npeak (alias for nch)   channel doping concentration
            n (alias for nj)   source/drain junction emission coefficient
            php (alias for pbsw)   source/drain sidewall junction capacitance built in potential
            ld (alias for lint)   length reduction parameter
            wd (alias for wint)   width reduction parameter
            xl   channel length reduction in meters due to masking and etching effects
            xw   channel width reduction in meters due to masking and etching effects
            lmlt   length shrink factor
            wmlt   diffusion layer and width shrink factor
            del   channel length reduction
            rs   source ohmic resistance
            rsc   additional source resistance due to contact resistance
            rd   drain ohmic resistance
            rdc   additional drain resistance due to contact resistance
            is   bulk junction saturation current
            cbd   zero bias bulk-drain junction capacitance
            cbs   zero bias bulk-source junction capacitance
            tt   transit time
    • Variable nopolyfitcheck added. If the variable is set then checking Gauss-Jordan elimination results is skipped when calculating the interpolating polynomial. Fitting curves which generates very large polynomial coefficients lead to numerical errors and interpolation therefore fails. To get at least inaccurate results nopolyfitcheck can be used.
    • subs option added into BJT model for modelling lateral transistor geometry. subs = 1 defines vertical transistor and subs = -1 defines lateral transistor respectively. For npn transistors vertical geometry is default, while lateral geometry is default for pnp transistors. Vertical and lateral geometry differ in connection of parasite substrate capacitance to collector (vertical - there is Csc) or base (lateral - there is Cbs).
  • Version 2.1 (date built: 4. October 2001)
    • nmirror option added into constrained simplex optimisation method. Option defines number of points mirrored in each iteration.
    • stop_cost option added into optimisation procedure. Option can be set/unset with optimize options command. The optimisation procedure is stopped if cost function value is lower than stop_cost value.
    • Instance parameter m (number of devices in parallel) added for BSIM3v3 MOSFET model (level=7). Default value: m=1.
    • The BSIM3 version 2 MOSFET device model was added for compatibility reasons. It is specified as level=47 in .model statement.
    • BSIM4 device model (level=8) upgraded to version 4.2.0.
    • Changed syntax for optimize parameter command.
    • Fixed a bug when the expression given for the voltage of non-linear dependent source is constant. In this case non-linear dependent source becomes an independent voltage source.
    • Normal (gaussian) distribution of parameter values added for random search (Monte Carlo optimisation method).
    • Added the nodeset and ic commands for dynamically setting nodesets and initial conditions.
    • Instance parameter m (number of parallel instances) added for resistors, capacitances, inductances, diodes, bipolar transistors, JFETs (level=1), MESFETs and MOSFETs (level=1). It defines number of devices in parallel. Default value: m=1.
    • Allocated memory control. Exact number of allocated bytes can be obtained by rusage command.
    • Syntax $&vector_name[index1,index2] fixed.
    • Temperature dependency added for JFET level=1 model (parameters bex and betatce).
    • Generation recombination noise source added for JFET level=1 model (parameters kgr, tau and ea).
    • Smarter autoscale for plot, better labeling.
    • Nutmeg function unwrap() added for phase unwrapping.
    • Added arithmetic substitution to nutmeg (by using {expression}).
    • Closed leaks asociated with temporary storage and vector or parse tree parameters in SPICE3 devices
    • Rewrite of subcircuit expansion and error messaging for the netlist parser.
    • Added subcircuit parameter passing.
    • Improved nutmeg listing function, provides many information on subcircuits.
    • Added plot command keywords quickappend (doesn't autoscale at append) and autoscale (manual triggering of autoscale).
    • Memory leak tracking added. To turn it on, type set memtrack. All allocations are tracked starting from the moment you turn it on. If memory tracking is on and you leave the program by typing quit, the unreleased memory information is dumped into a file named memdump.dbg in the current working directory. Send this file to the developers if your spice seems to leak memory (if after doing unalias *, undefine *, destroy all, optimize reset and delcirc all, calling rusage shows that more than 200k-300k memory is allocated). Note that in memory tracking mode SPICE runs about 2x slower and the actual memory consumption increases dramatically due to internal memory tracker structures. Memory allocated by the memory tracker for its internal purposes is not tracked. When the memory tracker is off, it doesn't have an impact on performance.
    • The simulator is now up to 50% faster and NUTMEG runs up to 25% faster.
    • Smarter file lookup for .include and .lib.
    • Added the .netclass and .endn keywords to the netlist parser. By means of netclasses failure mode analysis and cornerpoint analysis can be performed.
    • Added the netclass command to NUTMEG for selecting the type of netlist.
    • Subcircuit parameters can be accessed by using @name[param]. Subcircuit parameters can also be altered (let). The alter command doesn't work on subcircuit parameters.
    • Closed leaks in the netlist parse tree parser (B sources).
    • Added the optimize setparams command for setting the parameter values back to the values stored in the optimizer after a netclass rebuild is called.
  • Version 2.03    (date built: 12. October 2000)
    • Fixed interpolate() function.
    • Fixed crash when destroy all was called after multiple source commands.
    • Added the nameplot command for renaming a plot.
    • Added the support for keywords next and previous for the setplot command.
    • Added min(), max() and sum() functions to Nutmeg.
    • Fixed analysis clause in optimize. Loops (while, ...) now work with optimize.
    • optimize parameter has two new options now: log and lin. log sets logarithmic scale for a parameter. It is reccomended for parameters with wide ranges (let's say 1e-6 to 1e2). In most cases it improves convergence of the optimisation algorithm. lin sets linear scale as in older versions.
    • Elitism was added to the genetic optimisation algorithm (optimize method ... elitism ...).
    • 'set badcktfree' now makes the simulator release the circuit if it contains any errors.
    • 'set badcktstop' prevents the simulator from running the commands in the .control block on loading the circuit if the circuit contains any errors.
    • Fixed DC sweep so it doesn't give convergence problem messages when LIN, DEC and OCT sweep is used.
    • Plot name matching in expressions (plot.vector) now looks for an exact match and not prefix match (i.e. dc doesn't match dc1).
    • Fixed the way plots get enumerated. Previously two tran and two ac analyses produced plots tran1, tran2, ac2 and ac3. Now plots tran1, tran2, ac1, ac2 are produced. Actually the largest number found after plot name plus 1 is used as the postfix number.
    • Complete rewrite of the file sourcing. Added .lib clause support (HSPICE). Added hierarchical error reporting during parse.
    • Complete revision of the digital.cm library. Worst crashes fixed. Added examples that demonstrate the use of the digital.cm code models.
    • '-o filename' option now logs terminal window activity to a file specified by user and displays it in the terminal window at the same time. Logging can be temporarily disabled by selecting Edit/Logging from the menu.
    • Added menu option Control/Stop Execution that stops the current simulation and Nutmeg script.
    • Fixed signal handling. On segmentation violation and other fatal signals SPICE now displays an error message and waits for the user to press any key before the program is terminated. This way the user has time to examine the output before the window is closed.
    • Fixed binary operations when for complex scalar right operand the result was wrong if left operand was a vector.
    • 'let' command now releases the previous vector and creates a new vector if the assignement is not made into some elements of the vector. This way let behaves like in all other normal programming languages.
    • Added the vector[|low, high] operator (operator [| ]). This operation selects the elements from the vector for which the value of the scale is between low and high.
    • Added graph tagging. Tagging is achieved with commands 'plot create ...', 'plot append ' and 'plot destroy ' commands. When the usual 'plot' command is used or if an iplot is created, graphs are tagged automatically (for plot with 'plotn' and for iplot with 'iplotn').
    • Smarter refresh with 'plot append ...'.
    • Added functions floor(), ceil() and round() to Nutmeg.
    • Added 'optimize reset' command for cleaning up optimize settings.
    • Fixed x^y operation for B source, e.g. 2^v(1) previously didn't work. Now even v(1)^v(2) works.
    • Added the vector[%real_index] operator. It selects the point from the vector for which the index is equal to real_index (used with cursors). If real_index is not an integer number, the value is calculated using linear interpolation.
    • Added the 'cursor' command that can be used for manipulating digital oscilloscope style cursors for various waveform measurements.
    • Parameters function and order for independent voltage and current sources are now read-only. To change the order of a transient source, simply assign a vector to the coeffs parameter (let @vsrc[coeffs]=(1;9;0.1)). To change the type of the transient source, use sin (or sine), pulse, exp. pwl or sffm as parameter name instead of coeffs (to make a pulse source sinusoidal, type let @vsrc[sin]=(1;2;50)).
    • Eliminated the need for a CR in the last line of the source.
    • Fixed problems with the define command.
    • Parameters AF and KF are now showed correctly for JFET.
  • Version 2.02    (date built: 27. June 2000)
    • Fixed edit behaviour for Windows. 'edit' command starts an editor asynchronously. The spice circuit file must be sourced manually to simulate the changes. The same was done in Linux although we are still having problems with spice3 binary creating a zombie every time the editor is invoked. Fortunately all zombies die after the main SPICE window is closed.
    • Fixed the crash when using 'let @...' or 'let @@...'.
    • Added support for simulator parameters in let (e.g. 'let @@@temp=15' is equivalent to 'set temp=15'.
    • Fixed parser so that refering to vector range now works (e.g. a[2,8]).
    • Fixed crash when SPICE2 style nodenames (e.g. (2,3)) in subcircuits caused the simulator to crash due to wrong subcircuit expansion. The origin of the crash was in releasing code model structures. Subcircuit expansion sucks bigtime. We must rewrite it sometime. Anyway to make such circuits work, simply remove parenthesis and commas around node names.
    • Fixed crash caused by an attempt to access a vector after loading of first circuit failed.
    • Fixed crash during analysis when a current source was left dangling.
    • Fixed crash in UNIX version when loading a DOS CR-LF .cir file.
    • Fixed skipping leading spaces and tabs. Long netlist lines (>255 chars) don't crash the simulator now.
    • Old subcircuit expansion was completely removed. 'set oldsubcktexpand' has no effect now.
    • Added support for global nodes in subcircuits (HSPICE style). A global node is not considered to be an internal subcircuit node when it appears in subcircuit definition thus it is not expanded with subcircuit name. An example of a global node is node '0' (ground node). To make a node global use the .global option:
             .global node1 node2 ....
             
    • Fixed a bug when stop frequency lower than start frequency for ac analysis resulted in zero length vectors.
    • Fixed a bug when start and stop frequency were the same for ac analysis, SPICE would enter and infinite loop.
    • Note that NUTMEG is case sensitive. In case you want to be sure, write everything in lowercase.
    • Fixed CM vector parameter defaulting. s_xfer code models should work now without int_ic parameter given.
    • Fixed convergence problems with s_xfer code model when using UIC with tran analysis.
    • Fixed d_state code model so it doesn't crash if the state file is not found.
    • In case a circuit contains errors, the .control block is not executed. If the badcktfree variable is set, the circuit is immediately removed from memory after errors are found.
    • Added the ; operator. Now a vector can be constructed in Nutmeg from its components (e.g. 'let a=(1;2;3;c)' concatenates 1, 2, 3 and c).
    • Added icstep option. See more in a brief explanation of how initial conditions work .
    • Fixed simulator options METHOD (possible values: TRAP or GEAR) and MAXORD (1..6). Gear algorithm now really works. TRAP supports only orders 1 and 2. Anything more (or less) results in 2 (or 1). GEAR supports orders from 1 to 6.
  • Version 2.01    (date built: 16. May 2000)
    • Enhanced plot syntax so multiple 'vs' options can be supplied.
    • Added variables for controlling the plot window (plotwinwidth, plotwinheight, plotwininfo, plotautoident).
    • Added support for manual vector identification in plot window. This is now the default. Use 'set plotautoident' to restore vesion 2.0 behaviour.
    • Fixed a bug in TF analysis. Vector names for results are now input_impedance, output_impedance and transfer_function.
    • Fixed POLY sources so they really work now. SPICE2 syntax is now completely supported.
    • Added BSIM4 device model (level=8), version 4.0.0.
    • Updated BSIM3SOI device model to 2.1 (DD, FD) and 2.2 (PD) (now levels 9-11).
    • Fixed BSIM3v3.2.2 problem when BSIM3v3.2.2 models were giving incorrect results in simulations following the first simulation of a circuit.
    • Fixed 2-dimensional DC sweep that was broken by the general DC sweep enhancements.
    • Added support for Solaris i386 and SPARC platforms.
    • Released sources for code model libraries (.cm) along with makefiles.
    • Added suffixes for constants in B sources (mili, micro, ...).
    • If a circuit contains errors, structures that were created by loading the circuit are released.
    • Turned on DEVdelete and DEVmDelete capability in the source so the information about models and instances can be released from memory.
    • Added MOS6delete and MOS6mDelete functions.
    • Added DEVunsetup driver function for BSIM3v3.2.2.
    • Added releasing of internal G, body and charge nodes for BSIM4 in BSIM4unsetup.
    • Added releasing of internal debug nodes for BSIM3SOI DD, FD and PD models in unsetup function. TODO: releasing body and temperature nodes.
    • BSIM2 model temperature defaulting is fixed. It used to default to 27 degrees Celsius no matter what the circuit temperature was set to. TEMP parameter now defaults to circuit temperature. Since this parameter is stored in degrees Celsius (normally temperatures are stored in Kelvin) the value is converted by subtracting CONSTCtoK from the CKTnomTemp.
  • Version 2.0    (date built: 7. April 2000)
    • DC sweep of an arbitrary instance/model parameter, global temperature or nominal temperature in lin or log fashion.
    • Improved let command now supports instance/model parameters. Vector parameter components are also supported.
    • Instance/model parameters can be used in arbitrary expressions.
    • Improved print command can print vector data without a header and index column (easier exporting of data).
    • XSPICE extesions added (code modelling, improved convergence control, POLY sources, mixed-mode simulation).
    • An error in the state resolution table for digital nodes was fixed. The original table in the Georgia-Tech version of XSPICE is asymmetric. This is of course a total nonsense. You can take a look at the fixed table and send us your comments. We fixed it to our best knowledge and by studying carefully the original XSPICE manuals.
    • Templates for building your own code models in C.
    • siminfo command for checking the simulator status.
    • cmload command for loading XSPICE code models and user defined nodes from dll files (.cm files).
    • Printing support for SPICE terminal window and plot windows.
  • Version 1.2    (date built: 17. December 1999)
    • parameters coeffs (coefficients of time-depended value), distof1 and distof2 for independent sources can be changed with alter command and viewed with show command.
    • indexing of vector components.
    • calling extern executable in backquotes. Extern executable generates a sequence of Nutmeg commands on standard output. The commands are read and performed. The last character output from the executable has to be EOF.
    • The BSIM3 version 3.2.2 MOSFET SPICE model was added. It is specified as level=7 in .model statement.
    • The BSIM3SOI MOSFET SPICE model was added. Dynamic depletion BSIM3SOI model version 2.0 is specified as level=8 in .model statement. Fully depleted BSIM3SOI model version 2.0 is specified as level=9 in .model statement. And Partially depleted BSIM3SOI model version 2.0.1 is specified as level=10 in .model statement.
    • The spec command written by Anthony Parker, Macquarie University, was added.
    • The PS FET model developed by Anthony Parker and David Skellern was added. It is specified as level=2 in .model statement for JFET device.
    • repeat loop inside some other loop.
    • Complete rewrite of the plot and iplot commands.
  • Version 1.0    (date built: 18. October 1999)
    • Berkeley's 3f4 patch was applied (the unofficial SPICE 3f5 patch).
    • The original source code was slightly modified. Those modifications enabled the use of new standard C libraries which came with the compiler.
    • SpiceOpus was ported to the Windows 95/98/NT operating systems and to the Linux operating system.
    • The graphical part of the program was rewritten for Windows 95/98/NT and for Linux operating systems.
    • A significant number of memory leaks were tracked down and fixed. There were lots of cases where it was not clear who owned a piece of dynamically allocated data and so the original code would not free up the data by default. Some instability was also caused in cases when several structures point to the same dynamically allocated pieces of data.
    • cd command without HOME variable.
    • the $&vector_name syntax used when a vector is referenced as a variable.
    • alter command when syntax @device[parameter] is used and when it is used to change a model parameter (alter #modelname parameter = expression).
    • dereferencing NULL pointers, use of uninitialised pointers and multiple freeing of the same part of memory.
    • binary mode in write and load command.
    • time in rusage command.
    • the temperature of the circuit set by temp variable.
    • the save command.
    • saving of branch currents through voltage sources in resulting plots.
    • showing capacitance values for cgs, cgd and cgb with show command for level=1 MOSFETs.
    • Timestep too small error in transient analysis. The original Berkeley source code stops the analysis, when the time delta is less than 10-9 * maximum stepsize.
    • The new optimize command was added.

bullet Mission statement

It is our ambition to transfer optmization methods from a theoretical level to real life circuit design. SpiceOpus light is by no means just a side product of our scientific work - it serves two major purposes:
  1. Gathering research feedback. We encourage everybody to use SpiceOpus light freely so that users discuss their simulation problems with us. In this way our research work stays in touch with reality!
  2. Higher education. SPICE is well established as a teaching / learning tool. Hopefully students all over the world will benefit greatly from our free circuit simulator.
At the same time we continue our research work on the SpiceOpus code, which is now also focused on new methods and algorithms for increasing numerical stability and computational speed.

Your SpiceOpus team

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