Name |
CM or UDN |
Description |
climit |
CM |
Controlled limiter block. The limits are controlled by two inputs (one for
high limit and one for low limit). Offset and gain can be specified for the
input. The linear range has a lower limit that is set by the user
(limit_range parameter). limit_range can be specified either as an absolute
range (default) or percent of difference between upper and lower limit.
Smoothing is used in the transition from linear part to limiting in order
to avoid convergence problems. Smoothing is specified by upper_delta and
lower_delta parameters.
|
divide |
CM |
A two-quadrant analog divider. It has a numerator and a denominator input and
an output. Offset and gain can be specified for both inputs and the output.
The denominator is limited to a value above zero specified as den_lower_limit.
The limit is approached through a quadratic smoothing function. The domain of
this function can be specified as a fraction of the lower limit (default) or as
an absolute value.
|
d_dt |
CM |
Differentiator. Output offset and gain can be specified. Output can be limited
if out_lower_limit or out_upper_limit parameters are specified. The incremental
value of output at which smoothing occurs (when limitng is used) is specified
by the limit_range parameter.
Do not use this model in a feedback loop in order to provide an integration
function since it doesn't check for truncation errors. Use the integrate model
instead.
|
gain |
CM |
A simple gain block. Its parameters are gain, input_offset and output_offset.
|
hyst |
CM |
A hysteresis buffer block. The in_low and in_high specify the center value
around which the block operates. Output values are limited to out_upper_limit
and out_lower limit. The lower transition slope starts at in_lower-hyst and
ends at in_upper-hyst. The upper transition slope starts at in_lower+hyst and
ends at in_upper+hyst. Smoothing is performed at the transition from slope
to limiting. The smoothing is specified by the input_domain parameter and can
be given either as an absolute value or as percent of difference between in_high
and in_low. The type of the input_domain parameter is defined by the fraction
boolean parameter.
|
ilimit |
CM |
A current limiter block. This is actually a high level model for an opamp.
The input signal is taken from the in port. in_offset and gain are applied to
this voltage giving veq. Then it is limited between values from the pos_pwr
and neg_pwr ports. If the result is greater than the out port voltage, a
sourcing current flows from the output pin. In the opposite case a sinking
current flows into the output pin. The output resistance depends on the
polarity of the current flow (r_out_source, r_out_sink). The source/sink
current is limited by the i_limit_source and i_limit_sink parameters. The
output current is reflected on the pos_pwr/neg_pwr ports as current.
v_pwr_range controls the smoothing just before veq rises above pos_pwr or
falls below neg_pwr. i_source_range and i_sink_range specify the range at
which the sourcing/sinking current is smoothed. For veq-vout below r_out_domain
and above -rout_domain the output resistance is interpolated between r_out_source
and r_out_sink.
|
int |
CM |
Integrator block. Input offset and gain can be specified. The output can be
limited. When the output is limited, the transition to limiting is smoothed
in the limit_range below out_upper_limit and above out_lower_limit smoothing
is performed. The integrator can be given an output initial condition.
|
limit |
CM |
Limiter block. input_offset and gain are applied to the input signal and the
result is limited to out_lower_limit and out_upper_limit. limit_range specifies
the output range in which smoothing occurs. It can be given either as percent or
as an absolute value (controlled by the fraction boolean parameter).
|
mult |
CM |
in_offset array and in_gain array is applied to the vaues from the in vector port.
The results are then multiplied together, out_gain is applied and then out_offset
is added. The result is sent to the out port.
|
oneshot |
CM |
The value is taken at the cntl_in port and applied to the cntl_array and pwl_array
that describe the pulse width with respect to the cntl_in. The clk_in port triggers
the pulse. Trigger level is determined by the clk_trig parameter. pos_edge_trig
parameter determines the edge of the clk_in signal that triggers the output pulse
when clk_in reaches the clk_trig level. The output starts to rise with rise_delay
and rises to its final value after rise_time. pulse_width+fall_delay later the
output starts to fall and falls to its initial value after fall_time.
The retrig parameter specifies if it is possible to retrigger the output after it
was already triggered once. If the clear input is above clk_trig, the state of the
oneshot is cleared and it is prepared for a new triggering cycle.
|
pwl |
CM |
Piecewise linear transfer function. The x and the y array specify the transfer
function between input and output. Smoothing is applied to corners in the
input_domain range. The smoothing can be given either as a percent or as an
absolute value.
|
sine |
CM |
Controlled sine wave oscillator. The cntl_array and freq_array specify the
transformation of input signal into output frequency. A sine signal is
generated at the output with the calculated frequency. The out_low and
out_high parameters specify the valley and the peak value for the output
sine waveform.
|
slew |
CM |
A simple slew rate follower block. The rise_slope limits the rising slope and
the fall_slope limits the fall slope of the output signal. The units for the
slope limits are V/s or A/s.
|
square |
CM |
Controlled square wave oscillator (see sine CM). The cntl_array and freq_array
specify the transformation of input signal into output frequency. A square signal
is generated at the output with the calculated frequency. The out_low and
out_high parameters specify the valley and the peak value for the output
waveform. duty_cycle, rise_time and fall_time determine along with the calculated
frequency the output waveform.
|
summer |
CM |
The in_offset array is added to the in vector port inputs. The results are then
multiplied with the gains form the in_gain array and added together. The sum is
multiplied by out_gain and out_offset is added. The result is sent to the out port.
|
s_xfer |
CM |
A s-domain transfer function between out port and in port. in_offset and gain are
applied to the input signal. The signal is filtered using a s-domain transfer
function. The transfer function is described by the num_coeff and den_coeff
arrays. The first element of these two arrays is the one that belongs to the
highest order in the numerator/denominator s-domain polynomial. Initial conditions
can be provided for the integrators using a vector parameter int_ic. The
denormalized_freq parameter is used to transform the frequency. For instance a
set of coefficients for a low-pass filter with cut-off frequency at 1Hz can be
given in num_coeff and den_coeff and then transformed by the CM to a filter with
cut-off frequency at 100Hz by setting the denormalized_freq parameter to 100.
|
triangle |
CM |
Controlled triangle wave oscillator (see sine CM). The cntl_array and freq_array
specify the transformation of input signal into output frequency. A triangle signal
is generated at the output with the calculated frequency. The out_low and
out_high parameters specify the valley and the peak value for the output
waveform. duty_cycle parameter specifies the rise time duty cycle for the signal.
|
Name |
CM or UDN |
Description |
adc_bridge |
CM |
Analog-to-digital node bridge with vector input and vector output ports.
|
dac_bridge |
CM |
Digital-to-analog node bridge with vector input and vector output ports.
|
d_and |
CM |
AND gate with vector input and single output.
|
d_buffer |
CM |
Single input/single output buffer.
|
d_dff |
CM |
D-type flip-flop with input, clock, async. set, async. reset, out and inverted out.
As parameters you can specify rise_delay, fall_delay, set_delay, reset_delay,
clk_delay, initial_state, data_load, clk_load, set_load and reset_load.
|
d_dlatch |
CM |
D-type latch with input, enable, set, reset, out and inverted out.
It has the same parameters as d_dff except that instead of clk_delay
it has enable_delay.
|
d_fdiv |
CM |
Frequency divider. The number of input cycles for high output are set with the
high_cycles parameter. The divide factor is set by the div_factor parameter.
Output initial count value can also be set using the i_count parameter.
|
d_inverter |
CM |
Digital inverter.
|
d_jkff |
CM |
JK-type flip-flop. Similar to d_dff except that instead of one input it has a J
and a K input.
|
d_nand |
CM |
NAND gate with vector input and single output.
|
d_nor |
CM |
NOR gate with vector input and single output.
|
d_openc |
CM |
Digital one-bit-wide open collector buffer.
|
d_opene |
CM |
Digital one-bit-wide open emitter buffer.
|
d_or |
CM |
OR gate with vector input and single output.
|
d_osc |
CM |
Controlled digital oscillator. The cntl_in analog input along with the cntl_array
and freq_array parameters is used to determine the output signal frequency.
duty_cycle parameter determines the output duty cycle. init_phase determines
the initial phase of the output signal in degrees. rise_delay and fall_delay
specify the delays of the rising and falling edge of the signal.
|
d_pulldown |
CM |
Generates a RESISTIVE strength ZERO level at the node to which it is connected.
|
d_pullup |
CM |
Generates a RESISTIVE strength ONE level at the node to which it is connected.
|
d_ram |
CM |
Random-Access Memory. Ports: data_in and data_out (both vector), adress (vector),
write_en, select (chip select),
|
d_source |
CM |
Digital source. The output sequence is read from a file.
|
d_srff |
CM |
SR-type flip-flop. Similar to d_jkff except the instead if J and K input it has
S and R input.
|
d_srlatch |
CM |
SR-type latch. Similar to d_dlatch, except that instead of single input it has
S and R input.
|
d_state |
CM |
Digital state machine with vector in, clock, reset and vector out. The state
transition table is read from a file.
|
d_tff |
CM |
T-type flip-flop. Similar to d_dff except that it has a T input instead of a
D input.
|
d_tristate |
CM |
Tristate buffer with input, enable and output.
|
d_xnor |
CM |
XNOR gate with vector input and single output.
|
d_xor |
CM |
XOR gate with vector input and single output.
|
Name |
CM or UDN |
Description |
aswitch |
CM |
Smooth transition analog switch. It is a resistor that varies either logaritmically
or linearly between specified values of the controlling input.
|
capacitor |
CM |
A CM capacitor with voltage inital condition and support for supply ramping.
|
cmeter |
CM |
A capacitance to voltage convertor that converts the total capacitance seen on
its input into output voltage.
|
core |
CM |
A H-B core model. Current through this model stands for magnetic flux (B*area)
and voltage across it for magnetomotive force (H*length). Used in conjunction
with the lcouple model for modelling coupled electric and magnetic circuits. It
has two modes of operation. In mode 1 it works as a B-H transfer function
determined by the H_array and B_array parameters. In mode 2 it operates as a
hysteresis block between H and B (see hyst CM).
|
aswitch |
CM |
Smooth transition analog switch. It is a resistor that varies either logaritmically
or linearly between specified values of the controlling input.
|
inductor |
CM |
A CM inductor with current inital condition and support for supply ramping.
|
lcouple |
CM |
Inductive coupling. Used in conjunction with the core model. The mmf_out port
connects to the magnetic part of the circuit and the l port to the electric
part of the curcuit. It has only one parameter: number of turns.
|
lmeter |
CM |
A inductance to voltage convertor that converts the total inductance seen on
its input into output voltage.
|
potentiometer |
CM |
A potentiometer with two pot connections and a wiper connection. With the
parameters the total resistance, wiper position, type (lin, log) and
log multiplier (number of decades between wiper position 1 and position 0)
can be set.
|
zener |
CM |
Simple Zener diode model.
|